补全以下D触发器VHDL程序。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY dff IS PORT(CLK:IN STD_LOGIC; D:IN STD_LOGIC; Q:OUT STD_LOGIC);END dff;ARCHITECTURE bhv OF dff ISBEGIN PROCESS(_______) BEGIN IF CLK'EVENT AND CLK='1' THEN Q<=D; END IF; END PROCESS;END bhv;
A、CLK;
B、D;
C、Q;
D、dff
发布时间:2024-09-28 22:56:49